1. Field of the Invention
The present invention generally relates to testing of digital designs defining integrated circuits in a hardware description language and, more specifically, to creating standard test environments for digital designs.
2. Description of the Related Art
The proliferation of modern electronics into our everyday life is due in large part to the existence, functionality and relatively low cost of advanced integrated circuits. As technology moves ahead, the sophistication and, consequently, the complexity of design processes of integrated circuits continually increases.
An important aspect of designing a complex integrated circuit is the ability to thoroughly test the design of the integrated circuit to verify that the design complies with desired architectural, performance and design parameters. Verifying the logical correctness of a digital design and debugging the design, if necessary, are important steps in most digital design processes.
Integrated circuits are tested either by actually building networks or by simulating networks on a computer. Testing a complex integrated circuit requires the generation of a large number of instruction sequences to assure that the integrated circuit behaves properly under a wide variety of circumstances. Accordingly, testing has become a very costly and time-consuming segment of the overall design process as designs become increasingly complex. Since the fabrication of integrated circuits requires considerable-time and correction of mistakes is quite costly, it becomes necessary to test and simulate a design before the design is actually built.
Prior to testing, a designer creates a high-level description of an integrated circuit utilizing a hardware description language (HDL), such as VHDL or Verilog. VHDL is a higher-level language for describing the hardware design of complex integrated circuits. The overall circuit design is frequently divided into smaller parts, hereinafter referred to as design entities, which are individually designed, often by different designers.
FIG. 10 illustrates an exemplary design of an entity 1200 of an integrated circuit as described using a HDL according to the state of the art. Entity 1200 comprises a plurality of interfaces 1220, 1230, 1240, and 1250 and an architecture 1260. In VHDL, entity 1200 may further comprise one ore more configurations (not shown). Each Interface 1220, 1230, 1240 and 1250 comprises a plurality of input and output ports, each input port for receiving an input signal 1270 and each output port for providing an output signal 1280. A port may correspond to a pin on a corresponding integrated circuit or an edge connector on a board, and so on. The architecture 1260 describes the function of entity 1200. Accordingly, if the entity 1200 exemplarily represents a NAND-gate, architecture 1260 would describe how the output signal 1280 of the NAND-gate is created using appropriate input signals 1270. In a minimum configuration, entity 1200 may only comprise one interface having one input port and one output port.
Different entities of a digital design, for example, a plurality of entities 1200 according to FIG. 10, may be combined in a hierarchical manner to create an overall model. The hierarchical design technique is very useful in managing the enormous complexity of an overall design. Another advantage of this approach is that errors in a design entity are easier to detect when that entity is tested in isolation.
A problem arises, however, when the overall model is tested as a whole. Compound errors may occur which mask other individual errors. Further, the enormity of modern digital design complexity makes the errors in each design entity difficult to recognize. Therefore, although the hierarchical nature of VHDL eases the development and modeling phases of complex designs, problems with obtaining accurate and comprehensive test results of the overall design remain unresolved.
A useful method of addressing design complexity is to test digital designs at several levels of abstraction. At the functional level, system operation is described in terms of a sequence of transactions between registers, adders, memories and other functional units. Testing at the functional level is utilized to verify the high-level design of high-level systems. At the logical level, a digital system is described in terms of logic elements such as logic gates and flip-flops. Testing at the logic level is utilized to verify the correctness of the logic design. At the circuit level, each logic gate is described in terms of its circuit components such as transistors, impedances, capacitances, and other such devices. Testing at the circuit level provides detailed information about voltage levels and switching speeds.
For testing the design description, a designer may create a testbench. Such a testbench defines a test circuit and is constructed using the HDL. The testbench normally comprises the entity to be tested, i.e., a corresponding entity description, bus-functional models for driving the interfaces of the entity described by the entity description and an observer for observing the testing results. The bus-functional models and the observer are themselves separate modules. The testbench is used to apply stimulus to the design description and to verify whether the design operates as expected. The testbench is only used to verify input and output of the entity and is, accordingly, interface, i.e., hardware specific. Thus, the testbench has no architectural knowledge of the entity.
In current design processes, the testbench is manually generated by the designer and may then be instantiated by testcases for testing the corresponding entity description. However, manually creating testbenches for a large number of entity descriptions of a complex digital design is very time consuming and cumbersome for the designer. Furthermore, when migrating from one abstraction level to another in a digital design process, e.g., from the logical level to the circuit level, a testbench created at the logical level for testing a specific entity description may not be useable for testing the specific entity description at the circuit level as, for instance, corresponding interfaces of the entity description have been modified. Consequently, testbenches must either be modified or new testbenches must be created.
Therefore, there is a need to improve the creation of testing environments for digital designs in order to test and simulate a digital design more efficiently and effectively before the design is actually build.
The present invention generally is directed to a method, system and article of manufacture for testing of digital designs defining integrated circuits in a HDL and, more specifically, for creating standard test environments for digital designs. A digital design may comprise one or more entity descriptions describing different entities or blocks of the integrated circuit in the HDL. Tags are added to each entity description and used to generate procedure calls and a testbench for testing the corresponding entity.
One embodiment provides a method of creating an entity description for use in an automated testing environment, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function. The method comprises, for at least one port of the plurality of ports, associating at least one specific procedure call with the at least one port, the specific procedure call defining the pre-determined function of the at least one port.
Another embodiment provides a method of generating a procedure call from an entity description, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function. The method comprises: providing a plurality of build-in rules for constructing procedure calls; and providing a plurality of port description tags in the entity description, each port description tag associated with a specific port of the interface and comprising: at least one indication of a specific procedure call defining the pre-determined function of the associated specific port; and at least one parameter indicating a specific build-in rule for constructing the specific procedure call. The method further comprises, for at least one port description tag of the plurality of port description tags: determining the associated specific port, the at least one indication of a specific procedure call and the at least one parameter; determining the specific build-in rule from the plurality of build-in rules using the at least one determined parameter; and generating the specific procedure call using the at least one determined indication of the specific procedure call, the determined specific build-in rule and the determined associated specific port.
Still another embodiment provides a method of generating a testbench for testing an entity of an integrated circuit, the entity comprising at least one interface having a plurality of ports each associated with a pre-determined function, the entity being defined by an entity description in a hardware description language. The method comprises: providing a plurality of port description tags in the entity description, each port description tag associated with a port of the interface; providing a plurality of build-in rules for constructing procedure calls; generating at least one procedure call using at least one build-in rule of the plurality of build-in rules and at least one port description tag of the plurality of port description tags, the at least one procedure call defining the pre-determined function of the port associated with the at least one port description tag; and generating the testbench using the plurality of port description tags, at least one portion of the plurality of build-in rules and the at least one created procedure call.
Still another embodiment provides a computer-readable medium containing a program which, when executed, performs an operation of generating a procedure call from an entity description, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function. The operation comprises: providing a plurality of build-in rules for constructing procedure calls; and accessing a plurality of port description tags in the entity description, each port description tag associated with a specific port of the interface and comprising: at least one indication of a specific procedure call defining the predetermined function of the associated specific port; and at least one parameter indicating a specific build-in rule for constructing the specific procedure call. The operation further comprises, for at least one port description tag of the plurality of port description tags: determining the associated specific port, the at least one indication of a specific procedure call and the at least one parameter; determining the specific build-in rule from the plurality of build-in rules using the at least one determined parameter; and generating the specific procedure call using the at least one determined indication of the specific procedure call, the determined specific build-in rule and the determined associated specific port.
Still another embodiment provides a computer-readable medium containing a program which, when executed, performs an operation of generating a testbench for testing an entity of an integrated circuit, the entity comprising at least one interface having a plurality of ports each associated with a pre-determined function, the entity being defined by an entity description in a hardware description language. The operation comprises: accessing a plurality of port description tags in the entity description, each port description tag associated with a port of the interface; providing a plurality of build-in rules for constructing procedure calls; generating at least one procedure call using at least one build-in rule of the plurality of build-in rules and at least one port description tag of the plurality of port description tags, the at least one procedure call defining the pre-determined function of the port associated with the at least one port description tag; and generating the testbench using the plurality of port description tags, at least one portion of the plurality of build-in rules and the at least one generated procedure call.
Still another embodiment provides a computer program product comprising a procedure call generator for generating a procedure call from an entity description, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function; and a signal bearing medium containing the procedure call generator. The procedure call generator comprises: a plurality of build-in rules for constructing procedure calls; an accessing unit for accessing a plurality of port description tags in the entity description, each port description tag associated with a specific port of the interface and comprising at least one indication of a specific procedure call defining the pre-determined function of the associated specific port; and at least one parameter indicating a specific build-in rule for constructing the specific procedure call; a determining unit for determining, for at least one port description tag of the plurality of port description tags, the associated specific port, the at least one indication of a specific procedure call, the at least one parameter and the specific build-in rule from the plurality of build-in rules using the at least one determined parameter; and a generating unit for generating the specific procedure call using the at least one determined indication of the specific procedure call, the determined specific build-in rule and the determined associated specific port.
Still another embodiment provides a computer program product comprising a testbench generator for generating a testbench for testing an entity of an integrated circuit, the entity comprising at least one interface having a plurality of ports each associated with a pre-determined function, the entity being defined by an entity description in a hardware description language; and a signal bearing medium containing the testbench generator. The testbench generator comprises: a plurality of build-in rules for constructing procedure calls; an accessing unit for accessing a plurality of port description tags in the entity description, each port description tag associated with a port of the interface; a generating unit for generating at least one procedure call using at least one build-in rule of the plurality of build-in rules and at least one port description tag of the plurality of port description tags, the at least one procedure call defining the pre-determined function of the port associated with the at least one port description tag; and the testbench using the plurality of port description tags, at least one portion of the plurality of build-in rules and the at least one generated procedure call.
Still another embodiment provides a computer, comprising a memory and a processor adapted to execute contents of the memory. The memory contains at least a procedure call generator for generating at least one procedure call from an entity description, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function; the at least one procedure call defining the pre-determined function of at least one port of the plurality of ports.
Still another embodiment provides a computer, comprising a memory and a processor adapted to execute contents of the memory. The memory contains at least a testbench generator for generating a testbench for testing an entity of an integrated circuit, the entity comprising at least one interface having a plurality of ports each associated with a pre-determined function, the entity being defined by an entity description in a hardware description language.
Still another embodiment provides a method of generating logic for an entity of an integrated circuit, the entity comprising at least one interface having a plurality of ports each associated with a pre-determined function, the entity being defined by an entity description in a hardware description language. The method comprises: providing a plurality of port description tags in the entity description, each port description tag associated with a port of the interface; providing a plurality of build-in rules for constructing logic; and generating logic using at least one build-in rule of the plurality of build-in rules and at least one port description tag of the plurality of port description tags, the logic defining an architecture of the entity and the pre-determined function of the port associated with the at least one port description tag.
Still another embodiment provides a computer-readable medium containing a program which, when executed, performs an operation of generating logic for an entity of an integrated circuit, the entity comprising at least one interface having a plurality of ports each associated with a pre-determined function, the entity being defined by an entity description in a hardware description language. The operation comprises: accessing a plurality of port description tags in the entity description, each port description tag associated with a port of the interface; providing a plurality of build-in rules for constructing logic; and generating logic using at least one build-in rule of the plurality of build-in rules and at least one port description tag of the plurality of port description tags, the logic defining an architecture of the entity and the pre-determined function of the port associated with the at least one port description tag.
Still another embodiment provides a computer, comprising a memory and a processor adapted to execute contents of the memory. The memory contains at least a logic generator for generating logic for an entity of an integrated circuit, the entity comprising at least one interface having a plurality of ports each associated with a pre-determined function, the entity being defined by an entity description in a hardware description language.